与电子系统和集成电路的情况一样,传统硬件安全是围绕着占主导地位的CMOS技术发展的。随着各种新兴技术的兴起,其主要目的是克服CMOS技术在扩展性和功耗方面的限制,因此有了改进硬件的独特机会。本文将对硬件安全进行全面介绍。
关键词:硬件安全、自旋电子学、记忆电阻器、碳纳米管、纳米线晶体管、3D集成、2.5D集成、逆向工程、篡改
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2.1 运行时的数据安全
电子产品中数据处理的机密性、完整性和可用性受到各种威胁场景的影响,如未经授权的数据访问或修改、侧信道和故障注入攻击、物理读取和探测攻击。
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[2] E. Brier, C. Clavier, and F. Olivier, “Correlation power analysis with a leakage model,” in Proc. Cryptogr. Hardw. Embed. Sys., 2004. https://doi.org/10.1007/978- 3-540-28632-5_2
[3] P. Bayon et al., “Fault model of electromagnetic attacks targeting ring oscillatorbased true random number generators,” J. Cryptogr. Eng., vol. 6, no. 1, pp. 61–74, 2016. https://doi.org/10.1007/s13389-015-0113-2
[4] P. Qiu, D. Wang, Y. Lyu, and G. Qu, “VoltJockey: Breaching TrustZone by software-controlled voltage manipulation over multi-core frequencies,” in Proc. Comp. Comm. Sec., 2019, pp. 195–209. https://doi.org/10.1145/3319535.3354201
[5] V. van der Veen et al., “Drammer: Deterministic rowhammer attacks on mobile platforms,” in Proc. Comp. Comm. Sec., 2016, pp. 1675–1689. https://doi.org/10. 1145/2976749.2978406
[6] G. D. Natale, E. I. Vatajelu, K. S. Kannan, and L. Anghel, “Hidden-delay-fault sensor for test, reliability and security,” in Proc. Des. Autom. Test Europe, 2019, pp. 316–319. https://doi.org/10.23919/DATE.2019.8714891
[7] B. Karp, M. Gay, O. Keren, and I. Polian, “Security-oriented code-based architectures for mitigating fault attacks,”inProc. DCIS, 2018, pp. 1–6.https:// doi.org/10.1109/DCIS.2018.8681476
[8] J. Dutertre et al., “Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model,” in Proc. Worksh. Fault Diag. Tol. Cryptogr., 2018. https://doi.org/10.1109/FDTC.2018.00009
[9] M. Rostami, F. Koushanfar, and R. Karri, “A primer on hardware security: Models, methods, and metrics,” Proc. IEEE, vol. 102, no. 8, pp. 1283–1295, 2014. https: //doi.org/10.1109/JPROC.2014.2335155
[10] J. Knechtel, S. Patnaik, and O. Sinanoglu, “Protect your chip design intellectual property: An overview,” in Proc. Conf. Omni-Layer Intell. Sys., 2019, pp. 211–216. https://doi.org/10.1145/3312614.3312657
[11] L. Alrahis et al., “UNSAIL: Thwarting oracle-less machine learning attacks on logic
locking,” Trans. Inf. Forens. Sec., vol. 16, pp. 2508–2523, 2021. https: // doi.org/10.1109/TIFS.2021.3057576
[12] L. Li and A. Orailoglu, “Piercing logic locking keys through redundancy identification,” in Proc. Des. Autom. Test Europe, 2019. https://doi.org/10.23919/DATE. 2019.8714955
[13] C. McCants. (2016) Trusted integrated chips (TIC) program. https: //www.ndia.org/-/media/sites/ndia/meetings-and-events/divisions/systemsengineering/past-events/trusted-micro/2016-august/mccants-carl.ashx
[14] K. Vaidyanathan et al., “Building trusted ICs using split fabrication,” in Proc. Int. Symp. Hardw.-Orient. Sec. Trust, 2014, pp. 1–6. https://doi.org/10.1109/HST.2014. 6855559
[15] F. Imeson, A. Emtenan, S. Garg, and M. V. Tripunitara, “Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation,” in Proc. USENIX Sec. Symp., 2013, pp. 495–510. https://www.usenix.org/conference/usenixsecurity13/technicalsessions/presentation/imeson
[16] J. Knechtel et al., “Toward physically unclonable functions from plasmonicsenhanced silicon disc resonators,” J. Lightwave Tech., vol. 37, pp. 3805–3814, 2019. https://doi.org/10.1109/JLT.2019.2920949
[17] M. M. Sabry Aly et al., “The N3XT approach to energy-efficient abundant-data computing,” Proc. IEEE, vol. 107, no. 1, pp. 19–48, 2019. https://doi.org/10.1109/ JPROC.2018.2882603
[18] X. Wang and Y. Chen, “Spintronic memristor devices and application,” in Proc. Des. Autom. Test Europe, 2010, pp. 667–672. https://doi.org/10.1109/DATE.2010. 5457118
[19] S. Matsunaga et al., “Fabrication of a nonvolatile full adder based on logic-inmemory architecture using magnetic tunnel junctions,” Applied Physics Express, vol. 1, no. 9, p. 091301, 2008. https://doi.org/10.1143/APEX.1.091301
[20] C. Subramaniam et al., “Carbon nanotube-copper exhibiting metal-like thermal conductivity and silicon-like thermal expansion for efficient cooling of electronics,” Nanoscale, vol. 6, pp. 2669–2674, 2014. https://doi.org/10.1039/C3NR05290G
[21] S. S. Iyer, “Three-dimensional integration: An industry perspective,” MRS Bulletin, vol. 40, no. 3, pp. 225–232, 2015. https://doi.org/10.1557/mrs.2015.32
[22] D. Fick et al., “Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 cores in 3D stacked 130 nm CMOS,” J. Sol.-St. Circ., vol. 48, no. 1, pp. 104–117, 2013. https://doi.org/10.1109/JSSC.2012.2222814
[23] D. H. Kim et al., “3D-MAPS: 3D massively parallel processor with stacked memory,” in Proc. Int. Sol.-St. Circ. Conf., 2012, pp. 188–190. https://doi.org/10. 1109/ISSCC.2012.6176969
[24] A. Shilov. (2018) AMD previews EPYC rome processor: Up to 64 Zen 2 cores. https://www.anandtech.com/show/13561/amd-previews-epyc-romeprocessor-up-to-64-zen-2-cores
[25] C. C. Lee et al., “An overview of the development of a GPU with integrated HBM on silicon interposer,” in Proc. Elec. Compon. Tech. Conf., 2016, pp. 1439–1444. https://doi.org/10.1109/ECTC.2016.348
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